Detail page for fpu family

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Submitter:Paolo Marin
Suite:Miller-Marin
Domain:Formal Verification
Description: Blackbox BMC encoding of various modifications of an IEEE-754 compliant pipelined double precision floating point unit that supports four basic operations (+,-,*,/), multiple rounding modes and exceptions (VHDL code available at opencores.org). The instances contain about 21.000 gates and 2.700 latches.
Number of instances:398
Results:
Instances: