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Detail page for Debug family
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Submitter:
Hratch Mangassarian
Suite:
Mangassarian-Veneris
Domain:
Formal Verification
Description:
The Debug family consists of Design Debugging instances, which ask whether or not a certain erroneous circuit design, given a set of its failing responses, can be "fixed" by changing the functionality of one gate.
Number of instances:
38
Results:
2020 - Track 1
2019 - Track 1
2018 - Track 1
2018 - Track 5
2017 - Track 1
2017 - Track 2
2016 - Track 1
2016 - Track 2
2016 - Track 5
2016 - Track 6
2016 - Track 7
2010 - Track 1
2008 - Track 1
2007 - Track 1
Instances:
c1_Debug_s3_f1_e1_v1
c1_Debug_s3_f1_e1_v2
c1_Debug_s3_f1_e1_v3
c1_Debug_s3_f2_e1_v1
c1_Debug_s3_f2_e1_v2
c1_Debug_s3_f2_e1_v3
c1_Debug_s5_f1_e1_v1
c1_Debug_s5_f1_e1_v2
c1_Debug_s5_f1_e1_v3
c2_Debug_s3_f1_e1_v1
c2_Debug_s3_f1_e1_v2
c2_Debug_s3_f1_e1_v3
c2_Debug_s3_f2_e1_v1
c2_Debug_s3_f2_e1_v2
c2_Debug_s3_f2_e1_v3
c2_Debug_s5_f1_e1_v1
c2_Debug_s5_f1_e1_v2
c2_Debug_s5_f1_e1_v3
c3_Debug_s3_f2_e2_v2
c3_Debug_s3_f2_e2_v3
c4_Debug_s3_f1_e1_v1
c4_Debug_s3_f1_e1_v2
c4_Debug_s3_f1_e1_v3
c4_Debug_s3_f1_e2_v1
c4_Debug_s3_f1_e2_v2
c4_Debug_s3_f1_e2_v3
c4_Debug_s3_f2_e1_v1
c4_Debug_s3_f2_e1_v2
c4_Debug_s3_f2_e1_v3
c4_Debug_s3_f2_e2_v1
c4_Debug_s3_f2_e2_v2
c4_Debug_s3_f2_e2_v3
c4_Debug_s5_f2_e1_v1
c4_Debug_s5_f2_e1_v2
c4_Debug_s5_f2_e1_v3
c4_Debug_s5_f2_e2_v1
c4_Debug_s5_f2_e2_v2
c4_Debug_s5_f2_e2_v3
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