Suite Ayari

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Submitter: Ayari
Description: A family of problems related to the formal equivalence checking of partial implementations of circuits. For details, see Ayari, A. and Basin, D., 2000, July. Bounded model construction for monadic second-order logics. In International Conference on Computer Aided Verification (pp. 99-112). Springer, Berlin, Heidelberg.
Number of families: 5