Detail page for benchmark lut4_2_f2


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Submitter: Ling
Suite:Ling
Family:FPGA_PLB_FIT_SLOW
Domain:Formal Verification
Structure:Fixed
Classification:
  • 2016 - Track 1 : MEDIUM
  • 2016 - Track 2 : MEDIUM
  • 2016 - Track 5 : HARD
  • 2016 - Track 6 : EASY
  • 2016 - Track 7 : EASY
  • 2010 - Track 1 : MEDIUM
  • 2008 - Track 1 : MEDIUM
  • 2007 - Track 1 : MEDIUM
  • 2006 - Track 1 : MEDIUM
  • 2005 - Track 1 : MEDIUM
Description:

Results: